View MAX5931L_1350620.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max5930/max5931 +1v to +13.2v triple hot-swap controllers provide complete protection for multisupply systems. they allow the safe insertion and removal of circuit cards into live backplanes. these devices hot swap multiple supplies ranging from +1v to +13.2v, provided one supply is at or above +2.7v and only one supply is above 11v. the input voltage rails (channels) can be configured to sequentially turn-on/off, track each other, or have completely independent operation. the discharged filter capacitors of the circuit card pro- vide low impedance to the live backplane. high inrush currents from the backplane to the circuit card can burn up connectors and components, or momentarily collapse the backplane power supply leading to a system reset. the max5930/max5931 hot-swap controllers prevent such problems by gradually ramping up the output volt- age and regulating the current to a preset limit when the board is plugged in, allowing the system to stabilize safely. after the startup cycle is complete, on-chip com- parators provide variablespeed/bilevel protection against short-circuit and overcurrent faults, and provide immunity against system noise and load transients. the load is disconnected in the event of a fault condi- tion. the max5930/max5931 fault-management mode is selectable, allowing latched fault or autoretry after a fault condition. the max5930/max5931 offer a variety of options to reduce external component count and design time. all devices integrate an on-board charge pump to drive the gates of low-cost, external n-channel mosfets, an adjustable startup timer, and an adjustable current limit. the devices offer integrated features like startup cur- rent regulation and current glitch protection to eliminate external timing resistors and capacitors. the MAX5931L provides an open-drain, active-low status output for each channel, the max5931h provides an open-drain, active-high status output for each channel, and the max5930 status output polarity is selectable. the max5930 is available in a 24-pin qsop package, and the max5931 is available in a 20-pin qsop pack- age. all devices are specified over the extended -40? to +85? temperature range. applications features ? safe hot swap for +1v to +13.2v power supplies with any input voltage (v in_ ) 2.7v and only one v in_ > 11.0v ? adjustable circuit breaker/current-limit threshold from 25mv to 100mv ? configurable tracking, sequencing, or independent operation modes ? variablespeed/bilevel circuit-breaker response ? internal charge pumps generate n-channel mosfet gate drives ? inrush current regulated at startup ? autoretry or latched fault management ? programmable undervoltage lockout ? status outputs indicate fault/safe condition max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers ________________________________________________________________ maxim integrated products 1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 mode on3 lim2 in2 lim1 on1 on2 pol top view sense2 gate2 lim3 in3 stat1 gate1 sense1 in1 16 15 14 13 9 10 11 12 sense3 gate3 gnd bias stat3 latch tim stat2 qsop max5930 pin configurations ordering information 19-3032; rev 2; 3/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max5930 eeg -40? to +85? 24 qsop max5931 leep -40? to +85? 20 qsop max5931heep -40? to +85? 20 qsop variablespeed/bilevel is a trademark of maxim integrated products, inc. network switches, routers, hubs hot plug-in daughter cards raid solid-state circuit breakers power-supply sequencing/tracking base-station line cards portable computer device bays (docking stations) selector guide and typical operating circuit appear at end of data sheet. pin configurations continued at end of data sheet.
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd, unless otherwise noted.) in_ ..........................................................................-0.3v to +14v gate_.............................................................-0.3v to (in_ + 6v) bias (note 1) .............................................. (v in - 0.3v) to +14v on_, stat_, lim_ (max5930), tim, mode, latch, pol (max5930) ..........................-0.3v to (v in + 0.3v) sense_........................................................-0.3v to (in_ + 0.3v) current into any pin..........................................................?0ma continuous power dissipation (t a = +70?) 20-pin qsop (derate 9.1mw/? above +70?)............727mw 24-pin qsop (derate 9.5mw/? above +70?)............762mw operating temperature range ...........................-40? to +85? junction temperature .....................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v in_ = +1v to +13.2v provided at least one supply is larger than or equal to +2.7v and only one supply is > 11.0v, t a = -40? to +85?, unless otherwise noted. typical values are at v in1 = 12.0v, v in2 = 5.0v, v in3 = 3.3v, v on_ = +3.3v, and t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units power supplies in_ input voltage range v in_ at least one v in_ +2.7v and only one v in_ > 11.0v 1.0 13.2 v supply current i q i in1 + i in2 + i in3 , v on_ = 2.7v, v in_ = +13.2v, after stat_ high 2.5 5 ma current control t a = +25?c 22.5 25 27.5 lim_ = gnd (max5930), max5931 (note 4) t a = -40?c to +85?c 21.0 27.5 r lim_ = 10k ? (max5930) 80 125 slow-comparator threshold (v in_ - v sense_ ) (note 3) v sc,th r lim_ from lim_ to gnd (max5930) r lim_ x 7.5 x 10 -6 + 25mv mv 1mv overdrive 3 ms slow-comparator response time (note 4) t scd 50mv overdrive 130 ? fast-comparator threshold (v in_ - v sense_ ) v fc,th 2 x v sc , th mv fast-comparator response time t fcd 10mv overdrive, from overload condition 200 ns sense_ input bias current i b sense_ v sense_ = v in_ 0.03 1a mosfet driver r tim = 100k ? 8.0 10.8 13.6 r tim = 4k ? (minimum value) 0.30 0.4 0.55 startup period (note 5) t start tim floating (default) 5 9 14 ms note 1: v in is the largest of v in1 , v in2 , and v in3 .
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in_ = +1v to +13.2v provided at least one supply is larger than or equal to +2.7v and only one supply is > 11.0v, t a = -40? to +85?, unless otherwise noted. typical values are at v in1 = 12.0v, v in2 = 5.0v, v in3 = 3.3v, v on_ = +3.3v, and t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units charging, v gate_ = gnd, v in_ = +5v (note 6) 80 100 125 discharging, during startup 100 ? discharging, normal turn-off or triggered by the slow comparator after startup; v gate_ = 5v, v in_ = 10v, v on_ = 0v 237 average gate current i gate discharging, triggered by a fault after startup; v gate_ = 5v, v in_ = 10v, (v in_ - v sense_ ) > v fc,th_ (note 7) 30 50 120 ma gate-drive voltage v drive v gate_ - v in_ , i gate_ = 1? 4.9 5.3 5.6 v on comparator low to high 0.85 0.875 0.90 v on_ threshold v on_ , th hysteresis 25 mv on_ propagation delay 10mv overdrive 10 s on_ voltage range v on_ without false output inversion v in v on_ input bias current i bon v on_ = v in 0.03 1a on_ pulse-width low t unlatch to unlatch after a latched fault 100 s digital outputs (stat_) output leakage current v stat_ 13.2v 1 a output voltage low v ol_ pol = floating (max5930), i sink = 1ma 0.4 v undervoltage lockout (uvlo) uvlo threshold v uvlo startup is initiated when this threshold is reached by any v in_ and v on_ > 0.9v (note 8) 2.25 2.45 2.65 v uvlo hysteresis v uvlo , hyst 250 mv uvlo glitch filter reset time t d,gf v i n < v u v l o m axi m um p ul se w i d th to r eset 10 s uvlo to startup delay t d,uvlo time input voltage must exceed v uvlo before startup is initiated 20 37.5 60 ms input power-ready threshold v pwrrdy (note 9) 0.9 0.95 1.0 v input power-ready hysteresis v pwrhyst 50 mv logic and timing pol input pullup i pol pol = gnd (max5930) 2 4 6 a latch input pullup i latch latch = gnd 2 4 6 a mode input voltage v mode mode floating (default to sequencing mode) 1.0 1.25 1.5 v independent-mode selection threshold v indep , th v mode rising 0.4 v tracking-mode selection threshold v track , th v mode rising 2.7 v
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in_ = +1v to +13.2v provided at least one supply is larger than or equal to +2.7v and only one supply is > 11.0v, t a = -40? to +85?, unless otherwise noted. typical values are at v in1 = 12.0v, v in2 = 5.0v, v in3 = 3.3v, v on_ = +3.3v, and t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units mode input impedance r mode 200 k ? autoretry delay t retry delay time to restart after fault shutdown 64 x t start ms note 2: all devices are 100% tested at t a = +25?. limits over temperature are guaranteed by design. note 3: the slow-comparator threshold is adjustable. v sc,th = r lim x 7.5? + 25mv (see the typical operating characteristics ). note 4: the current-limit slow-comparator response time is weighed against the amount of overcurrent, the higher the overcurrent condition, the faster the response time (see the typical operating characteristics ). note 5: the startup period (t start ) is the time during which the slow comparator is ignored and the device acts as a current-limiter by regulating the sense current with the fast comparator (see the startup period section). note 6: the current available at gate is a function of v gate (see the typical operating characteristics ). note 7: after a fault triggered by the fast comparator, the gate is discharged by the strong discharge current. note 8: each channel input while the other inputs are at +1v. note 9: each channel input while any other input is at +3.3v. t ypical operating characteristics (typical operating circuits, q1 = q2 = q3 = fairchild fdb7090l, v in1 = +12.0v, v in2 = +5.0v, v in3 = +1v, t a = +25?, unless oth- erwise noted. channels 1 through 3 are identical in performance. where characteristics are interchangeable, channels 1 through 3 are referred to as x, y, and z.) 0 1 2 3 4 supply current vs. input voltage max5930 toc01 v inx (v) i in (ma) 068 24 10 12 14 v iny = v inz = 2.7v i inx + i iny + i inz i inx i iny + i inz 1.0 2.0 3.0 4.0 5.0 26 4810 12 14 total supply current vs. input voltage max5930 toc02 v in (v) i in (ma) i in = i in1 + i in2 + i in3 v in = v inx = v iny = v inz v on = v on1 = v on2 = v on3 v on = 0v v on = 3.3v 0 1.0 0.5 2.0 1.5 2.5 3.0 -40 85 supply current vs. temperature max5930 toc03 temperature ( c) i in (ma) 10 -15 35 60 i iny + i inz v on_ = v iny = v inz = 2.7v v inx = 2.8v i iny + i inz i inx
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers _______________________________________________________________________________________ 5 0 2 4 6 8 gate-drive voltage vs. input voltage max5930 toc04 v inx (v) v drivex (v) 068 24 10 12 14 v iny = v inz = 2.7v 0 30 90 60 120 150 gate charge current vs. gate voltage max5930 toc05 v gatex (v) gate charge current ( a) 010 51520 v onw = v iny = v inz = 2.7v v inx = 13.2v v inx = 5v v inx = 1v 0 40 120 80 160 200 gate charge current vs. temperature max5930 toc06 temperature ( c) gate charge current ( a) -40 35 10 -15 60 85 v onx = v iny = v inz = 2.7v v gatex = 0v v inx = 13.2v v inx = 5v v inx = 1v 0 2 1 4 3 5 6 020 strong gate discharge current vs. gate voltage max5930 toc07 v gatex (v) gate discharge current (ma) 8 41216 v inx = 13.2v v inx = 1v v inx = 5v v inx = 3.3v v onx = 0v v iny = v inz = 2.7v 0 2 1 4 3 5 6 -40 85 strong gate discharge current vs. temperature max5930 toc08 temperature ( c) gate discharge current (ma) 10 -15 35 60 v inx = 13.2v v inx = 5v v inx = 3.3v v inx = 1v v onx = 0v v iny = v inz = 2.7v 10 025507 5 100 125 1 0.1 0.01 0.001 0.0001 turn-off time vs. sense voltage max5930 toc09 v inx - v sensex (mv) turn-off time (ms) r limx = 100 ? slow-comparator threshold fast-comparator threshold turn-off time vs. sense voltage (expanded scale) max5930 toc10 v inx - v sensex (mv) turn-off time (ms) 10 0.1 1 20 25 30 35 40 45 50 r limx = 100 ? slow-comparator threshold 0 40 20 60 100 80 120 slow-comparator threshold vs. r limx max5930 toc11 r limx (k ? ) v sc,th (mv) 0 2 6 48 10 0 20 40 60 startup period vs. r tim max5930 toc12 r tim (k ? ) t start (ms) 0 100 200 400 300 500 t ypical operating characteristics (continued) (typical operating circuits, q1 = q2 = q3 = fairchild fdb7090l, v in1 = +12.0v, v in2 = +5.0v, v in3 = +1v, t a = +25?, unless oth- erwise noted. channels 1 through 3 are identical in performance. where characteristics are interchangeable, channels 1 through 3 are referred to as x, y, and z.)
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 6 _______________________________________________________________________________________ turn-off time slow-comparator fault max5930 toc13 v statx 2v/div v gatex 5v/div v inx - v sensex 25mv/div ac-coupled 0v 0v 1ms/div turn-off time fast-comparator fault max5930 toc14 v statx 2v/div v gatex 5v/div v inx - v sensex 100mv/div 0v 0v 0v 100ns/div startup waveforms fast turn-on (c gate = 0nf, c board = 1000 f) max5930 toc15 v onx 5v/div v gatex 10v/div v statx 5v/div i outx 2a/div v outx 5v/div 2ms/div startup waveforms slow turn-on (c gate = 0.22 f, c board = 1000 f) max5930 toc16 v on 5v/div v gatex 10v/div v statx 5v/div i outx 2a/div v outx 5v/div 2ms/div autoretry delay max5930 toc17 v gatex 2v/div 0v 0v 0v v outx 2v/div i outx 500ma/div 100ms/div turn-on in voltage-tracking mode max5930 toc18 v inx 2v/div 0v 0v v onx 2v/div 5v/div 4ms/div v pwrrdy v gatey v gatex t ypical operating characteristics (continued) (typical operating circuits, q1 = q2 = q3 = fairchild fdb7090l, v in1 = +12.0v, v in2 = +5.0v, v in3 = +1v, t a = +25?, unless oth- erwise noted. channels 1 through 3 are identical in performance. where characteristics are interchangeable, channels 1 through 3 are referred to as x, y, and z.)
xxxx max5930 toc19 v inx 2v/div 0v v onx 2v/div 5v/div 0v 4ms/div v gatey v gatex v pwrrdy turn-off in voltage-tracking mode xxxx max5930 toc20 v inx 2v/div v onx 2v/div 0v 5v/div 4ms/div v gatey v gatex turn-on in power-sequencing mode v pwrrdy 0v 0v xxxx max5930 toc21 v inx 2v/div v onx 2v/div 5v/div 0v 0v 0v 4ms/div v gatey v gatex turn-off in power-sequencing mode v pwrrdy max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers _______________________________________________________________________________________ 7 xxxx max5930 toc22 v inx 2v/div v onx 2v/div 5v/div 0v 4ms/div turn-on in independent mode v gatey v gatex 0v xxxx max5930 toc23 v inx 2v/div 0v v onx 2v/div 5v/div 0v 4ms/div turn-off in independent mode v pwrrdy v gatey v gatex 0 20 10 30 40 50 20 50 strong gate discharge current vs. overdrive max5930 toc24 v in_ - v sense_ (mv) gate discharge current (ma) 35 25 30 40 45 v inx = 5v v inx = 2.7v v onx = v in v gate = 5v after startup lim_ = gnd v inx = 12v t ypical operating characteristics (continued) (typical operating circuits, q1 = q2 = q3 = fairchild fdb7090l, v in1 = +12.0v, v in2 = +5.0v, v in3 = +1v, t a = +25?, unless oth- erwise noted. channels 1 through 3 are identical in performance. where characteristics are interchangeable, channels 1 through 3 are referred to as x, y, and z.)
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 8 _______________________________________________________________________________________ pin description pin max5930 max5931 name function 1 pol stat output-polarity select (see table 3 and the status output section) 21 on2 on/off channel 2 control input (see the mode section) 32 on1 on/off channel 1 control input (see the mode section) 4 lim1 channel 1 current-limit setting. connect a resistor from lim1 to gnd to set current-trip level. connect to gnd for the default 25mv threshold. do not leave lim1 open. 53 in1 channel 1 supply input. connect to a 1v to 13.2v supply voltage and to one end of r sense1 . bypass with a 0.1? capacitor to ground. 64 sense1 channel 1 current-sense input. connect sense1 to the drain of an external mosfet and to one end of r sense1 . 75 gate1 channel 1 gate-drive output. connect to gate of external n-channel mosfet. 86 stat1 op en- d r ai n s tatus s i g nal for c h annel 1. s tat1 asser ts w hen hot sw ap i s successful and t s t ar t has el ap sed . s tat1 d easser ts i f on 1 i s l ow , or i f channel 1 i s tur ned off for any faul t cond i ti on. 97 stat2 op en- d r ai n s tatus s i g nal for c h annel 2. s tat2 asser ts w hen hot sw ap i s successful and t s t ar t has el ap sed . s tat2 d easser ts i f on 2 i s l ow , or i f channel 2 i s tur ned off for any faul t cond i ti on. 10 8 tim startup timer setting. connect a resistor from tim to gnd to set the startup period. leave tim unconnected for the default startup period of 9ms. r tim must be between 4k ? and 500k ? . 11 9 latch latch/autoretry selection input. connect latch to gnd for autoretry mode after a fault. leave latch open for latch mode. 12 10 stat3 open-drain status signal for channel 3. stat3 asserts when hot swap is successful and t start has elapsed. stat3 deasserts if on3 is low, or if channel 3 is turned off for any fault condition. 13 11 bias supply reference output. the highest supply is available at bias for filtering. connect a 1nf to 10nf ceramic capacitor from bias to gnd. no other connections are allowed to bias. 14 12 gnd ground 15 13 gate3 channel 3 gate-drive output. connect to gate of external n-channel mosfet. 16 14 sense3 channel 3 current-sense input. connect sense3 to the drain of an external mosfet and to one end of r sense3 . 17 15 in3 channel 3 supply input. connect to a supply voltage from 1v to 13.2v and to one end of r sense3 . bypass with a 0.1? capacitor to ground. 18 lim3 channel 3 current-limit setting. connect a resistor from lim3 to gnd to set current-trip level. connect to gnd for the default 25mv threshold. do not leave lim3 open. 19 16 gate2 channel 2 gate-drive output. connect to gate of external n-channel mosfet. 20 17 sense2 channel 2 current-sense input. connect sense2 to the drain of an external mosfet and to one end of r sense2 . 21 18 in2 channel 2 supply input. connect to a 1v to 13.2v supply voltage and to one end of r sense2 . bypass with a 0.1? capacitor to ground.
detailed description the max5930/max5931 are circuit-breaker ics for hot- swap applications where a line card is inserted into a live backplane. the max5930/max5931 operate down to 1v provided one of the inputs is above 2.7v and only one supply is above 11v. normally, when a line card is plugged into a live backplane, the card? discharged fil- ter capacitors provide low impedance that can momen- tarily cause the main power supply to collapse. the max5930/max5931 reside either on the backplane or on the removable card to provide inrush current limiting and short-circuit protection. this is achieved by using external n-channel mosfets, external current-sense resistors, and on-chip comparators. the startup period and current-limit threshold of the max5930/max5931 can be adjusted with external resistors. figure 1 shows the max5930/max5931 functional diagram. the max5930 offers three programmable current limits, selectable fault-management mode, and selectable stat_ output polarity. the max5930 features fixed cur- rent limits, selectable fault-management mode, and fixed stat_ output polarity. mode the max5930/max5931 supports three modes of oper- ation: voltage-tracking, power-sequencing, and inde- pendent mode. select the appropriate mode according to table 1. voltage-tracking mode connect mode high to enter voltage-tracking mode. while in voltage-tracking mode, all channels turn on and off together. to turn all channels on: at least one v in_ must exceed v uvlo (2.45v) for the uvlo to startup delay (37.5ms). all v in_ must exceed v pwrrdy (0.95v). all v on_ must exceed v on,th (0.875v). no faults may be present on any channel. the max5930/max5931 turns off all channels if any of the above conditions are not met. after a fault-latched shutdown, cycle any of the on_ pins to unlatch and restart all channels. power-sequencing mode leave mode floating to enter power-sequencing mode. while in power-sequencing mode, the max5930/max5931 turn on and off each channel depending on the state of the corresponding v on_ . to turn on a given channel: at least one v in_ must exceed v uvlo (2.45v) for the uvlo to startup delay (37.5ms). all v in_ must exceed v pwrrdy (0.95v). the corresponding v on_ must exceed v on,th (0.875v). no faults may be present on any channel. the max5930/max5931 turn off all channels if any of the above conditions are not met. after a fault-latched shut- down, cycle any of the on_ pins to unlatch and restart all channels, dependent on the corresponding v on_ state. independent mode tie mode to gnd to enter independent mode. while in independent mode the max5930/max5931 provide complete independent control for each channel. to turn on a given channel: at least one v in_ must exceed v uvlo (2.45v) for the uvlo to startup delay (37.5ms). the corresponding v in_ must exceed v pwrrdy (0.95v). the corresponding v on_ must exceed v on,th (0.875v). max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers _______________________________________________________________________________________ 9 mode operation high (connect to bias) voltage tracking open voltage sequencing gnd independent table 1. operational mode selection pin max5930 max5931 name function 22 lim2 channel 2 current-limit setting. connect a resistor from lim2 to gnd to set current-trip level. connect to gnd for the default 25mv threshold. do not leave lim2 open. 23 19 on3 on/off channel 3 control input (see the mode section) 24 20 mode mode configuration input. mode is configured according to table 1 as soon as one of the in_ voltages exceeds uvlo and before turning on out_ (see the mode section). pin description (continued)
max5930/max5931 the max5930/max5931 turn off the corresponding channel if any of the above conditions are not met. during a fault condition on a given channel only, the affected channel is disabled. after a fault-latched shut- down, recycle the corresponding on_ inputs to unlatch and restart only the corresponding channel. startup period r tim sets the duration of the startup period from 0.4ms (r tim = 4k ? ) to 51ms (r tim = 500k ? ) (see the setting the startup period, r tim section). the default startup period is fixed at 9ms when tim is floating. the startup period begins after the turn-on conditions are met as described in the mode section, and the device is not latched or in its autoretry delay (see the latched and autoretry overcurrent fault management section). low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 10 ______________________________________________________________________________________ f ast comp slow comp f ast discharge q1 out1 2.45v bias and references startup oscillator timing oscillator charge pump device control logic v sc, th v fc, th r lim1 sense1 in1 gate1 r sense1 lim1* r tim l tim 1nf bias pol* r lim2 3ma 50ma 100 a uvlo uvlo f ast comp slow comp f ast discharge slow discharge slow discharge q2 out2 charge pump current control and startup logic current control and startup logic v sc, th v fc, th sense2 in2 gate2 r sense2 lim2* 100 a 3ma 50ma s tat2 s tat1 lim3* f ast comp slow comp f ast discharge q3 out3 f ault management operation mode charge pump on input comparators v sc, th v fc, th sense3 in3 gate3 r sense3 r lim3 3ma 50ma 100 a uvlo slow discharge current control and startup logic s tat3 *max5930 only. latch* mode on1 on2 on3 max5930 max5931 figure 1. functional diagram
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers ______________________________________________________________________________________ 11 on1 on2 on3 any in_ in2 in3 out1 * out3 * out2 * v uvlo (2.45v) v pwrrdy (0.95v) v pwrrdy (0.95v) v pwrrdy (0.95v) * the out_ discharge rate is a result of natural decay of the load resistance and capacitance. figure 2. voltage-tracking timing diagram (provided t d, uvlo requirement is met)
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 12 ______________________________________________________________________________________ on1 on2 on3 any in_ in2 in3 out1 out2 out3 v uvlo (2.45v) v pwrrdy (0.95v) v pwrrdy (0.95v) v pwrrdy (0.95v) * the out_ discharge rate is a result of natural decay of the load resistance and capacitance. * * * * figure 3. power-sequencing timing diagram (provided t d, uvlo requirement is met)
the max5930/max5931 limit the load current if an overcurrent fault occurs during startup instead of com- pletely turning off the external mosfets. the slow comparator is disabled during the startup period and the load current can be limited in two ways: 1) slowly enhancing the mosfets by limiting the mosfet gate-charging current. 2) limiting the voltage across the external current- sense resistor. during the startup period, the gate-drive current is limit- ed to 100? and decreases with the increase of the gate voltage (see the typical operating characteristics ). this allows the controller to slowly enhance the mosfets. if the fast comparator detects an overcurrent, the max5930/max5931 regulate the gate voltage to ensure that the voltage across the sense resistor does not exceed v su,th . this effectively regulates the inrush cur- rent during startup. figure 6 shows the startup waveforms. stat_ is assert- ed immediately after the startup period if no fault condi- tion is present. variablespeed/bilevel fault protection variablespeed/bilevel fault protection incorporates comparators with different thresholds and response times to monitor the load current (figure 7). during the startup period, protection is provided by limiting the load current. protection is provided in normal operation (after the startup period has expired) by discharging the mosfet gates with a strong 3ma/50ma pulldown current in response to a fault condition. after a fault, stat_ is deasserted. use the latch input to control whether the stat_ outputs latch off or autoretry (see the latched and autoretry fault management section). slow-comparator startup period the slow comparator is disabled during the startup period while the external mosfets are turning on. disabling the slow comparator allows the device to ignore the higher-than-normal inrush current charging the board capacitors when a card is first plugged into a live backplane. slow-comparator normal operation after the startup period is complete, the slow comparator is enabled and the device enters normal operation. the comparator threshold voltage (v sc,th ) is adjustable from 25mv to 100mv. the slow-comparator response time is 3ms for a 1mv overdrive. the response time decreases to 100? with a large overdrive. the variable-speed response time allows the max5930/max5931 to ignore low-amplitude momentary glitches, thus increasing sys- tem noise immunity. after an extended overcurrent condi- tion, a fault is generated, stat_ outputs are deasserted and the mosfet gates are discharged with a 3ma pull- down current. fast-comparator startup period during the startup period, the fast comparator regu- lates the gate voltages to ensure that the voltage across the sense resistor does not exceed the startup fast-comparator threshold voltage (v su,th ), v su,th is scaled to two times the slow-comparator threshold (v sc,th ). max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers ______________________________________________________________________________________ 13 figure 4. power-sequencing fault turn-off on1 = on2 = on3 overcurrent fault condition out1 out2 out3 * the out_ discharge rate is a result of natural decay of the load resistance and capacitance. * * *
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 14 ______________________________________________________________________________________ on1 on2 on3 in1 in2 in3 out1 out2 out3 v uvlo (2.45v) v pwrrdy (0.95v) v pwrrdy (0.95v) v pwrrdy (0.95v) * the out_ discharge rate is a result of natural decay of the load resistance and capacitance. t d,uvlo * * * figure 5. independent-mode timing diagram
fast-comparator normal operation in normal operation, if the load current reaches the fast- comparator threshold, a fault is generated, stat_ is deasserted, and the mosfet gates are discharged with a strong 50ma pulldown current. this happens in the event of a serious current overload or a dead short. the fast-comparator threshold voltage (v fc,th ) is scaled to two times the slow-comparator threshold (v sc,th ). this comparator has a fast response time of 200ns (figure 7). undervoltage lockout (uvlo) the uvlo prevents the max5930/max5931 from turning on the external mosfets until one input voltage exceeds the uvlo threshold (2.45v) for t d,uvlo . the max5930/max5931 use power from the highest input voltage rail for the charge pumps. this allows for more efficient charge-pump operation. the highest v in_ is pro- vided as an output at bias. the uvlo protects the external mosfets from an insufficient gate-drive volt- age. t d,uvlo ensures that the board is fully inserted into the backplane and that the input voltages are stable. the max5930/max5931 includes a uvlo glitch filter (t d,gf ) to reject all input voltage noise and transients. bringing all input supplies below the uvlo threshold for longer than t d,gf reinitiates t d,uvlo and the startup peri- od, t start . see figure 8 for an example of automatic turn-on function. latched and autoretry fault management the max5930 can be configured to either latch the external mosfets off or to autoretry (see table 2). toggling on_ below 0.875v for at least 100? clears the max5930/max5931 (latch = float) fault and reinitiates the startup period. similarly, the max5930/ max5931 (latch = gnd) turn the external mosfets off when an overcurrent fault is detected, then automat- ically restart after the autoretry delay that is internally set to 64 times t start . status outputs (stat_) the status (stat_) outputs are open-drain outputs that assert when hot swap is successful and t start has elapsed. stat_ deasserts if on_ is low or if the chan- nel is turned off for any fault condition. the polarity of the stat_ outputs is selected using pol for the max5930 (see table 3). tables 4 and 5 contain the max5930/max5931 truth tables. max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers ______________________________________________________________________________________ 15 figure 6. independent-mode startup waveforms t on v drive v gate_ v gate_ on_ s tat_ v th v out_ v out_ i load_ t start c board_ = large c board_ = 0 v fc,th r sense_ figure 7. variablespeed/bilevel response sense voltage (v in - v sense ) turn-off time v sc,th v fc,th (2 x v sc,th ) 3ms 130 s 200ns slow comparator f ast comparator
max5930/max5931 applications information component selection n-channel mosfets select the external mosfets according to the applica- tion? current levels. table 6 lists recommended com- ponents. the mosfet? on-resistance (r ds(on) ) should be chosen low enough to have a minimum volt- age drop at full load to limit the mosfet power dissi- pation. high r ds(on) causes output ripple if there is a pulsating load. determine the device power rating to accommodate a short-circuit condition on the board at startup and when the device is in autoretry mode (see the mosfet thermal considerations section). using these devices in latched mode allows the use of mosfets with lower power ratings. a mosfet typical- ly withstands single-shot pulses with higher dissipation than the specified package rating. table 7 lists some recommended mosfet manufacturers. sense resistor the slow-comparator threshold voltage is adjustable from 25mv to 100mv. select a sense resistor that caus- es a drop equal to the slow-comparator threshold volt- age at a current level above the maximum normal operating current. typically, set the overload current at 1.2 to 1.5 times the full load current. the fast-compara- tor threshold is two times the slow-comparator thresh- old in normal operating mode. choose the sense- resistor power rating to be greater than or equal to 2 x (i overload ) x v sc,th . table 7 lists some recommend- ed sense-resistor manufacturers. slow-comparator threshold, r lim (max5930) the slow-comparator threshold voltage is adjustable from 25mv to 100mv, allowing designers to fine-tune the current-limit threshold for use with standard-value sense resistors. low slow-comparator thresholds allow for increased efficiency by reducing the power dissi- pated by the sense resistor. furthermore, the low 25mv slow-comparator threshold is beneficial when operating with supply rails down to 1v because it allows a small percentage of the overall output voltage to be used for current sensing. the variablespeed/bilevel fault pro- tection feature offers inherent system immunity against load transients and noise. this allows the slow-com- parator threshold to be set close to the maximum nor- mal operating level without experiencing nuisance faults. to adjust the slow-comparator threshold, calcu- late r lim as follows: where v th is the desired slow-comparator threshold voltage. shorting lim_ to gnd sets v th to 25mv. do not leave lim_ open. r vmv a lim th = ? 25 75 . low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 16 ______________________________________________________________________________________ latch fault management floating fault condition latches mosfets off low autoretry mode table 2. selecting fault-management mode (max5930) pol stat_ low asserts low floating asserts high (open-drain) table 3. selecting stat_ polarity (max5930) figure 8. automatic turn-on when input voltages are above their respective undervoltage lockout threshold (provided t d,uvlo requirement is met) max5930 max5931 v 1 on1 on2 on3 gnd gnd on1 on2 on3 removable card backplane v 2 v 3
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers ______________________________________________________________________________________ 17 part channel 1 fault channel 2 fault channel 3 fault stat1/ gate1 * stat2/ gate2 * stat3/ gate3 * yes x x l/off l/off l/off x yes x l/off l/off l/off xx yes l/off l/off l/off xx x l/off l/off l/off max5930 (pol = 1), max5931h no no no h/on h/on h/on yes x x h/off h/off h/off x yes x h/off h/off h/off xx yes h/off h/off h/off xx x h/off h/off h/off max5930 (pol = 0), MAX5931L no no no l/on l/on l/on table 4. status output truth table: voltage-tracking and power-sequencing modes note: stat_ is asserted when hot swap is successful and t on has elapsed. stat_ is unasserted during a fault. channel 1 fault channel 2 fault channel 3 fault stat1/ gate1 stat2/ gate2 stat3/ gate3 yes yes yes unasserted/off unasserted/off unasserted/off yes yes no unasserted/off unasserted/off asserted/on yes no yes unasserted/off asserted/on unasserted/off yes no no unasserted/off asserted/on asserted/on no yes yes asserted/on unasserted/off unasserted/off no yes no asserted/on unasserted/off asserted/on no no yes asserted/on asserted/on unasserted/off no no no asserted/on asserted/on asserted/on table 5. status output truth table: independent mode * l = low, h = high. part number manufacturer description irf7413 11m ? , 8-pin so, 30v irf7401 22m ? , 8-pin so, 20v irl3502s international rectifier 6m ? , d 2 pak, 20v mmsf3300 20m ? , 8-pin so, 30v mmsf5n02h 30m ? , 8-pin so, 20v mtb60n05h motorola 14m ? , d 2 pak, 50v fds6670a 10m ? , 8-pin so, 30v nd8426a 13.5m ? , 8-pin so, 20v fdb8030l fairchild 4.5m ? , d 2 pak, 30v table 6. recommended n-channel mosfets
max5930/max5931 setting the startup period, r tim the startup period (t start ) is adjustable from 0.4ms to 50ms. the adjustable startup period feature allows sys- tems to be customized for mosfet gate capacitance and board capacitance (c board ). the startup period is adjusted with a resistor connected from tim to gnd (r tim ). r tim must be between 4k ? and 500k ? . the startup period has a default value of 9ms when tim is left floating. calculate r tim with the following equation: where t start is the desired startup period. startup sequence there are two ways of completing the startup sequence. case a describes a startup sequence that slowly turns on the mosfets by limiting the gate charge. case b uses the current-limiting feature and turns on the mosfets as fast as possible while still preventing a high inrush current. the output voltage ramp-up time (t on ) is determined by the longer of the two timings, case a and case b. set the startup timer (t start ) to be longer than t on to guarantee enough time for the output voltage to settle. case a: slow turn-on (without current limit) there are two ways to turn on the mosfets without reaching the fast-comparator current limit: if the board capacitance (c board ) is small, the inrush current is low. if the gate capacitance is high, the mosfets turn on slowly. in both cases, the turn-on time is determined only by the charge required to enhance the mosfet. the small 100? gate-charging current effectively limits the output voltage dv/dt. connecting an external capacitor between gate and gnd extends the turn- on time. the time required to charge/discharge a mosfet is as follows: where: c gate is the external gate to ground capacitance (figure 9), ? v gate is the change in gate charge, q gate is the mosfet total gate charge, i gate is the gate-charging/discharging current. in this case, the inrush current depends on the mosfet gate-to-drain capacitance (c rss ) plus any additional capacitance from gate to gnd (c gate ), and on any load current (i load ) present during the startup period. example: charging and discharging times using the fairchild fdb7030l mosfet if v in1 = 5v then gate1 charges up to 10.4v (v in1 + v drive ), therefore ? v gate = 10.4v. the manufacturer? data sheet specifies that the fdb7030l has approxi- mately 60nc of gate charge and c rss = 600pf. the max5930/max5931 have a 100? gate charging cur- rent and a 3ma/50ma normal/strong discharging cur- rent. c board = 6? and the load does not draw any current during the startup period. with no gate capaci- tor, the inrush current, charge, and discharge times are: i f pf aa t vnc a ms t vnc ma ms t vnc ma s inrush charge discharge normal discharge strong = + += = + = = + = = + = 6 600 0 100 0 1 0104 60 100 06 0104 60 3 002 0104 60 50 12 . . . . . . () () i c cc ii inrush board rss gate gate load = + + t cvq i gate gate gate gate = + ? r t pf tim start = 128 800 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 18 ______________________________________________________________________________________ component manufacturer phone website dale-vishay 402-562-3131 www.vishay.com sense resistors irc 704-264-8861 www.irctt.com fairchild 888-522-5372 www.fairchildsemi.com international rectifier 310-233-3331 www.irf.com mosfets motorola 602-224-3576 www.mot-sps.com/ppd table 7. component manufacturers
with a 22nf gate capacitor, the inrush current, charge, and discharge times are: case b: fast turn-on (with current limit) in applications where the board capacitance (c board ) is high, the inrush current causes a voltage drop across r sense that exceeds the startup fast-comparator threshold. the fast comparator regulates the voltage across the sense resistor to v fc,th . this effectively reg- ulates the inrush current during startup. in this case, the current charging c board can be considered con- stant and the turn-on time is: the maximum inrush current in this case is: figure 6 shows the waveforms and timing diagrams for a startup transient with current regulation (see the typical operating characteristics ). when operating under this condition, an external gate capacitor is not required. on comparators the on comparators control the on/off function of the max5930/max5931. on_ is also used to reset the fault latch (latch mode). pull v on_ low for 100?, t unlatch , to reset the shutdown latch. on_ also programs the uvlo threshold (see figure 10). a resistive-divider between v in_ , v on_ , and gnd sets the user-program- mable turn-on voltage. in power-sequencing mode, an rc circuit can be used at on_ to set the delay timing (see figure 11). using the max5930/max5931 on the backplane using the max5930/max5931 on the backplane allows multiple cards with different input capacitance to be inserted into the same slot even if the card does not have on-board hot-swap protection. the startup period can be triggered if in_ is connected to on_ through a trace on the card (figure 12). input transients the voltage at in1, in2, or in3 must be above v uvlo dur- ing inrush and fault conditions. when a short-circuit con- dition occurs on the board, the fast-comparator trips cause the external mosfet gates to be discharged at 50ma according to the mode of operation (see the mode section). the main system power supply must be able to sustain a temporary fault current, without dropping below the uvlo threshold of 2.45v, until the external mosfet is completely off. if the main system power supply collapses below uvlo, the max5930/max5931 force the device to restart once the supply has recovered. the mosfet is turned off in a very short time resulting in a high di/dt. the i v r inrush fc th sense = , t cvr v on board in sense fc th = , i f pf nf ama t nf v nc a ms t nf v nc ma ms t nf v nc ma s inrush charge discharge normal discharge strong = + += = + = = + = = + = 6 600 22 100 0 26 5 22 10 4 60 100 289 22 10 4 60 3 0 096 22 10 4 60 50 58 . . . . . . . () () max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers ______________________________________________________________________________________ 19 figure 10. adjustable undervoltage lockout gate_ sense_ v turn-on - (r 2 x r 1 ) v on , th r 2 on_ v in in_ r 1 r 2 max5930 max5931 figure 9. operating with an external gate capacitor gate_ sense_ gnd on_ r sense_ v out_ c gate c board v in_ in_ r pullup s tat_ max5930 max5931
max5930/max5931 backplane delivering the power to the external card must have low inductance to minimize voltage transients caused by this high di/dt. mosfet thermal considerations during normal operation, the external mosfets dissi- pate little power. the mosfet r ds(on) is low when the mosfet is fully enhanced. the power dissipated in nor- mal operation is p d = i load 2 x r ds(on) . the most power dissipation occurs during the turn-on and turn-off transients when the mosfets are in their linear regions. by taking into consideration the worst-case scenario of a continuous short-circuit fault, consider these two cases: 1) the single turn-on with the device latched after a fault: max5930/max5931 (latch = high or floating). 2) the continuous autoretry after a fault: max5930/ max5931 (latch = low). mosfet manufacturers typically include the package thermal resistance from junction to ambient (r ja ) and thermal resistance from junction to case (r jc ), which determine the startup time and the retry duty cycle (d = t start /(t start + t retry ). calculate the required tran- sient thermal resistance with the following equation: where i start = v su,th /r sense . z tt vi ja max jmax a in start () ? low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 20 ______________________________________________________________________________________ iny gatey inz gatez q1 r sensey sensey r sensez sensez q2 c boardz outy c boardy outz v y c 1 r 1 v en v z on off gnd max5930 max5931 on gnd v ony, th v onz, th t delay v en t 1 = -r 1 c 1 ln ( ) v en - v ony, th v en v on v y v z t 0 t 1 t 2 t 2 = -r 1 c 1 ln ( ) v en - v onz, th v en t delay = -r 1 c 1 ln ( ) v en - v ony, th v en - v onz, th figure 11. power sequencing: channel z turns on t delay after channel y
layout considerations to take full tracking advantage of the switch response time to an output fault condition, it is important to keep all traces as short as possible and to maximize the high-cur- rent trace dimensions to reduce the effect of undesirable parasitic inductance. place the max5930/max5931 close to the card? connector. use a ground plane to minimize impedance and inductance. minimize the current-sense resistor trace length (<10mm), and ensure accurate cur- rent sensing with kelvin connections (figure 13). when the output is short circuited, the voltage drop across the external mosfet becomes large. hence, the power dissipation across the switch increases, as does the die temperature. an efficient way to achieve good power dissipation on a surface-mount package is to lay out two copper pads directly under the mosfet pack- age on both sides of the board. connect the two pads to the ground plane through vias, and use enlarged copper mounting pads on the topside of the board. max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers ______________________________________________________________________________________ 21 figure 13. kelvin connection for the current-sense resistors sense resistor high-current path max5930 max5931 figure 12. using the max5930/max5931 on a backplane on_ in_ gate_ v in v out sense_ max5930 max5931 c board backplane power supply removable card with no hot-insertion protection 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 mode on3 in2 sense2 sense1 in1 on1 on2 top view gate2 in3 sense3 gate3 tim stat2 stat1 gate1 12 11 9 10 gnd bias stat3 latch max5931 qsop pin configurations (continued)
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers 22 ______________________________________________________________________________________ selector guide part current limit fault management stat_ polarity max5930eeg programmable selectable selectable MAX5931Leep fixed selectable asserted low max5931heep fixed selectable asserted high (open-drain) max5930 max5931 gnd q3 q2 q1 v 1 on1 on2 on3 gnd on1 out1 out2 *max5930 only. **optional component. out3 1nf 16v s tat1 s tat2 s tat3 bias tim mode pol* latch* lim3* lim2* lim1* in3 in2 in1 sense3 sense2 sense1 gate1 gate2 gate3 on2 on3 removable card backplane v 2 v 3 r sense1 r sense2 r sense3 r lim1 ** r lim2 ** r lim3 ** r lim ** t ypical operating circuit chip information transistor count: 7704 process: bicmos
max5930/max5931 low-voltage, triple, hot-swap controllers/ power sequencers/voltage trackers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch

▲Up To Search▲

Price & Availability of MAX5931L

	To Download MAX5931L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .